The present invention relates generally to memory integrated circuits. More particularly, the present invention relates to method and apparatus for high speed charging of core cell drain lines in a memory integrated circuit.
Conventional memory integrated circuits include an array of core cells. Each core cell stores one or more bits of information. Each core cell is independently addressable for writing and reading data. Each core cell includes one or more transistors suitable for retaining data. Each core cell is located at the intersection of a row or word line and a column or bit line, with a drain of one transistor coupled to a bit line. By applying appropriate voltages to the word line and the bit line, the data may be written in the core cell. By applying an appropriate word line voltage and selecting an appropriate bit line using decoding transistors, the current in the core cell may be detected to read the state of the data stored in the core cell. Common memory device types include flash, EPROM, EEPROM and others.
In reading the data in core cells, a large amount of time has been required to charge the capacitance associated with the drain of the core cell. This large drain capacitance is due to the large number of transistors coupled to the column line; capacitance due to routing the column line over other devices and the substrate; and the capacitance of the decoding transistors. Charging the drain line or bit line is a necessary part of sensing the state of the stored data in the selected core cell.
Sensing occurs by detecting a voltage change on the drain line. In one example, the drain line is charged to 0.5 volts. The desired core cell is selected by asserting its word line to a read voltage. This causes the core cell transistor to conduct a relatively low current (if it has been programmed) or a relatively high current (if it is un-programmed). The low current will cause a deflection in the bit line voltage to, for example, 0.55 volts. The high current will cause a bit line voltage deflection to 0.45 volts, for example. The sensing circuit must be able to reliably sense the voltage deflection of 0.05 volts. To minimize the time required to sense the state of the core cell, which is a key design goal for a memory device, the time required to charge the drain line to should be minimized.
In previous designs, the drain line or bit line has been charged using a circuit of ratioed transistors. These transistors are part of the sensing circuit. By selecting the relative sizes of the transistors as well as other physical properties, the precharge voltage (0.5 volts in the example above) can be set. The transistors are coupled to a selected bit line and given time to charge up the associated capacitance.
However, this previous charging circuit has required a design trade off. If the transistors are sized relatively small, a large voltage deflection (i.e., greater than the 0.05 volt deflection in the example above) is created. This improves the sense margin for the memory device, thereby improving its rejection of noise and its reliability. However, the small sized transistors are relatively weak and can not conduct enough current to rapidly charge the drain line. On the other hand, if the sizes of the transistors are increased to increase their current drive and shorten the charging time for the drain line, the voltage deflection during sensing is reduced (i.e., to less than the 0.05 volt deflection in the example above).
Accordingly, there is a need for a method and apparatus which provides a large voltage deflection on the drain line to maintain an adequate sense margin but which also provides high speed charging of the core cell drain lines.